Correctness is the driving force behind my research. Incorrect operation of silicon chips has lasting, and sometimes devastating, effects on computer systems and their manufacturers, from erroneous pace makers, to incorrect computation results, to security vulnerabilities affecting end users, to financial impact on the vendors. Correctness challenges are driven by the increasing complexity of such chips, with transistor counts soaring into the billions. These on-chip systems are large, distributed and complex; thus, a large number of interactions must be verified during the design process. As a result, verification effort has been steadily increasing, and on average, the industry spends more time in verification than design. My research brings a data science approach to verification. It uses machine learning to accelerate, automate and extend the reach of the verification process, providing decreased occurrence of - and increased resilience to - failures.